As memories grow faster, denser, and more complex, there is an increased demand for ABIST (Array Built-In Self-Test) structures for logic and memory fault detection offering high speed and high test coverage, while at the same time, consuming minimal area of a semiconductor chip. In addition, it is also highly desired to have a redundancy mechanism (word or bit line) to be combined therewith for repairability purposes. The combination of these two features will become more prevalent in the near future due to reasons that include testing cost, time and yield improvement. By way of example, to date, in conventional SRAM macros implementing these combined features, the replacement of defective lines with redundant lines is performed on product chips at the wafer level before burn-in and is limited to a single pass of fuse blow, as it will be explained herewith in conjunction with FIGS. 1 to 3.
FIG. 1 shows the block diagram architecture of a prior art SRAM macro 10 provided with an ABIST unit 11. A similar architecture is described in U.S. Pat. No. 5,173,906 of common assignee. The functional units shown in FIG. 1, either form part of a stand-alone SRAM or the SRAM macro of a logic array of an integrated circuit chip. In the latter case, the chip may include a plurality of such macros, each provided with its own dedicated ABIST unit. The integrated circuit chip described is part of a wafer fabricated in a very large scale integration (VLSI) semiconductor technology and is presumed to be designed according to level-sensitive scan design (LSSD) rules.
As known to those skilled in the art, the SRAM macro 10 shown in FIG. 1 has three basic modes of operation: A SYSTEM mode, in which the SRAM macro 10 operates normally, i.e., where the memory unit 12 is either read or written, using the data-in signals DATAIN1 to DATAINM, the SRAM address signals ADDIN1 to ADDINP, and the read/write control signal R/WIN (where in M and P are, respectively the bit widths of the data-in bus DATAIN and the SRAM address bus ADDIN). A second mode is required to satisfy LSSD requirements: the SCAN mode which is used for initializing/analyzing (SCAN-IN/SCAN-OUT) all the data of the latch pairs forming an LSSD chain. Finally, a third mode, the ABIST mode, in which the functionality of memory unit 12 is tested. It is a self-test which is first performed in a manufacturing environment before the chip is commercially released. A slightly different, more relaxed self-test is performed while the chip is incorporated in a system, for example, at the customer location, and thus in a system environment. As a result, the ABIST mode is used in a different environment referred to hereinafter as the ABIST manufacturing sub-mode and the ABIST system sub-mode.
In the ABIST mode, according to the fundamentals of the self-test technique, the ABIST unit 11 generates a plurality of test patterns. Each test pattern consists of a set of deterministic 0's and 1's that are first written into memory 12, read out and compared with an expected pattern. The test pattern sequences play a key role in exercising the memory unit 12 to verify if the memory unit 12 under test is functioning properly, i.e., to determine whether the READ and WRITE operations were successfully executed. To that end, the ABIST unit 11 generates self-test data signals STDATA, self-test address signals STADD, and the self-test read/write control signal STRW.
Three groups of multiplexers select the signals to be fed to the memory unit 12. They include either the external signals mentioned above which are generated outside the SRAM macro 10, namely, DATAIN1 . . . DATAINM, ADDIN1 . . . ADDINP, and R/WIN or, alternatively, internal self-test signals generated by the ABIST unit 11 previously mentioned, namely, the STDATA, STADD, and STRW signals. The multiplexers forming these three groups are respectively referenced as 13-1 to 13-M, 13'-1 to 13'-P, and 13". The selection is made by the ABIST control signal. Normally, external signals are selected when the ABIST signal is held at a logic "0", whereas when signals internally generated by the ABIST unit 11 are selected, it is held at a logic "1". The ABIST signal thus allows SRAM 10 to operate either in a SYSTEM mode or in an ABIST mode. The three groups of multiplexers, i.e., 13-1 to 13-M, 13'-1 to 13'-P, and 13" form multiplexer block 13. The outputs of the first and second groups are labelled DATA bus and ADD bus, with M and P as their respective bit widths. The output of multiplexer 13" is a single line that transports the R/W control signal that determines the READ/WRITE operating mode of memory 12.
The data-out signals that are outputted by memory 12 are stored in a plurality of data-out L1/L2 pairs of latches (14-1 to 14-M) forming the data-out shift register 14. Generally, these data-out latch pairs are incorporated into the memory 12. The data-out signals that are outputted by the L1 and L2 latch pairs are labelled DATAOUT1 to DATAOUTM (DATAOUT bus), and DOUT1 to DOUTM (DOUT bus), respectively.
In the ABIST mode, after performing a READ operation, expected data signals (EXDATA) are generated by ABIST 11 on the EXDATA bus and are compared in the data compression 15 via data-out signals DOUT1 to DOUTM. Typically, only four test patterns are used in each word of memory 12: alternating 0's and 1's, i.e., 0101 . . . 01 and 1010 . . . 10, all 0's and all 1's. Alternatively, there are only four self-test data signals, labelled STDATA0, STDATA1 and their respective complements. Because of the particular structure of these four test patterns, the data-out signals DOUT1 to DOUTM are divided into even and odd data-out signals. The even data-out signals that are outputted from the data-out shift register unit 14 are labelled DOUT2, DOUT4, . . . , DOUT2j, and likewise, the odd data-out signals are labelled DOUT1, DOUT3, . . . , DOUT(2j-1), wherein j is an integer equal to M/2, assuming that M is an even number. Since all the even and odd numbered bits of the data-out signals have simultaneously the same `0` or `1` value, only two expected data signals are required, each consisting of a single bit, EXDATA0 and EXDATA1. For instance, assuming that the data-out signals to be read on the DOUT bus are: 010101 . . . 01, the expected data signal EXDATA0 (for the even numbered bits) will be "1"0 and the expected data signal EXDATA1 (for the odd numbered bits) a "0". EXDATA0 and EXDATA1 are thus the expected results of the even and odd data-out signals, respectively. Finally, data compression unit 15 generates a signal labelled RESULT which is held at a "1" if a mismatch occurs during the comparison. By mismatch, it is to be understood that at least one data-out signal does not have the same logic value as its corresponding even or odd expected data generated by the ABIST structure 11. This mismatch is often caused by a defective word line in the memory unit 12 at a predetermined address. This mismatch is usually referred to as a "fail". Alternatively, if all data-out signals match the corresponding even or odd expected data signals (which means no fail is detected), the RESULT signal is held at "0". The RESULT signal, which is often referred to as the FAIL FOUND LAST CYCLE signal, indicates after completing a READ operation, whether the memory unit 12 at the current address is defective. The RESULT signal is thus indicative of the fail/no fail status of memory unit 12 on a cycle by cycle basis.
Another key component of the prior art SRAM macro 10 is the fail register unit 16. It is required because, in the ABIST manufacturing sub-mode, the addresses of the defective word lines have to be identified, then memorized for subsequent use in the SYSTEM mode. When the RESULT signal is raised to a logic "1", indicating the presence of a failure, the word portion of the current address generated by the ABIST unit 11 on the STADD bus, (labelled STADD*), is stored in a bank of pairs or latches of the fail address register 16. This stored word address thus corresponds to the address of a defective word line.
The ABIST unit 11 also generates a CNOOP (NOOP stands for NO OPERATION) signal to inhibit the ABIST self-test mode, when the totality of the test pattern sequences has been fully exercised on the memory unit 12. This signal is required when there is a plurality of SRAM macros embedded in a semiconductor chip. The macros may have different sizes that require varying durations for their respective test. The CNOOP signal generated by the ABIST unit of each SRAM macro allows the memory units of all macros to be simultaneously tested.
Clocking the SRAM macro 10 is achieved using standard procedures in accordance with LSSD rules. In the state of the art architecture of an SRAM, as illustrated in FIG. 1, clocking would normally be implemented by standard external LSSD clock signals labelled A, B, C, S, and CS (CHIP SELECT for a stand-alone SRAM chip or ARRAY SELECT for a SRAM macro). Note that the S clock signal, which is substantially the same as the B clock signal, is applied to the L2 latches of the latch pairs 14-1 to 14-M of the data-out shift register 14. In the ABIST manufacturing sub-mode, the clock and CS signals are derived from the tester. In the ABIST system sub-mode, these signals are derived from the system clock. The SCAN-IN (SI) signal is applied to the ABIST unit 11 according to the standard LSSD rules, as illustrated in FIG. 1. However, for sake of simplicity, the SCAN-OUT signal generated by ABIST 11 in response to the SCAN-IN signal to be applied to the next latch pair, etc., along the whole LSSD chain, is not shown. In the following description, only latches will be referred to, while it is clear that according to LSSD rules, they are in reality latch pairs. All these signals are directly applied to ABIST 11 and/or to the memory 12, except for the C clock and CS signals. The C clock signal is applied to one input of a 2-way AND gate 17A. The CS signal is applied to one input of the 2-way AND gate 17B. The CNOOP signal is applied to the second input of AND gates 17A and 17B as a gating signal in order to block, when needed, the transmission of the respective C clock and CS signal. This occurs when the self- test has been completed in the ABIST mode, and permanently in the SYSTEM mode. The A, B, and S clock signals are used during the SCAN mode, whereas the B, C, S and CS signals are used during the ABIST mode. The CS signal is used alone in the SYSTEM mode while the LSSD clock signals are held in a non-active state. Numeral 18 schematically illustrates the clock distribution scheme in the SRAM macro 10 and also includes the internal chip clock distribution network servicing it. This terminates the description of a state of the art SRAM macro provided with an ABIST structure.
Referring back to FIG. 1 illustrating a state of the art SRAM macro architecture, a typical word line redundancy mechanism will be briefly discussed. Note that a bit line or a block redundancy mechanism could be implemented just as well. For convenience sake, let the memory unit 12 be comprised of three blocks: a memory cell array 12A, a word and bit line decoder 12B and a comparator 12C. Memory cell array 12A is subdivided into a regular or standard array 12A' and a redundant array 12A". Let it be assumed that the redundant array 12A" contains q redundant word lines. The SRAM macro 10 further includes a storage unit 19 that contains non-volatile programmable elements, such as metal or polycristalline fuses. These elements store the addresses of the defective word lines of the regular array 12A' to be replaced by redundant word lines and to be referred hereinafter as the defective word addresses. As apparent from FIG. 1, all the connections between these elements are standard connections.
Compare circuit 12C receives signals through a first bus, referred to as the ADD* bus, which transports the word portion of the address available on the ADD bus, and a second bus which contains all the defective word line addresses, (referred to hereinafter as the DADD bus), from the storage unit 19. In addition to the defective word line addresses, the DADD bus also includes q "flag" lines. Each "flag" line transports a signal that indicates the presence of an active defective word line. As well known to those skilled in the art, the basis of the redundancy mechanism is a comparison function that reroutes addressing of defective word lines of the regular array 12A' towards redundant word lines of the redundant array 12A". At each cycle, the current address is applied to the decoder 12B. Similarly and in parallel, the word portion carried on bus ADD* is compared in comparator 12C with the defective word addresses stored in storage unit 19. This comparison aims at determining whether the current word address corresponds to the address of a defective word line. If found defective, the word line of the regular array 12A' needs replacing by one of the q redundant word lines of the redundant array 12A". This selection is achieved by comparator 12C which activates the appropriate selection signal R1, . . . , Rq. Selection signals R1, . . . , Rq are directed from comparator 12C to the redundant array 12A" via the R1/Rq bus. In addition, a control signal labelled MATCH is also sent to the decoder block 12B to inhibit the latter. This only occurs if a match exists between the current address present on the ADD* bus and one of the addresses present in the DADD bus. The MATCH signal controls the final stage of the word and bit line decoder 12B and inhibits only the word portion thereof.
A second key component of the redundancy mechanism is the fail register unit 16. In the ABIST manufacturing sub-mode, the addresses of the defective word lines once identified, are temporarily stored in said fail address register 16, and then permanently memorized in storage unit 19. These stored defective word addresses will be subsequently and permanently used in the SYSTEM mode. Obviously, there is a one to one correspondence between the addresses stored in the storage unit 19 and in the fail address register unit 16.
The storage process will be explained in more details in conjunction with FIG. 2, which schematically illustrates the circuit implementation of a conventional fail address register unit 16, such as described in U.S. Pat. No. 5,173,906. It is comprised of two blocks 16A and 16B and of an optional third block 16C located in the data compression unit 15. Block 16A includes address load register 21 which receives the STADD* signal bus from the ABIST unit 11, i.e., the word portion of the self-test addresses. The output bus of register 21 is connected in parallel to the input of q fail address registers 22-1 to 22-q. Note that a number of fail address registers different from the number q of redundant word lines could be envisioned as well. The role of the failed address register 22-1 is to store the first defective (failing) word address, followed by the second, etc., until fail address register 22-q stores the qth defective word address. To each of these fail address registers is associated a corresponding "flag" latch (referenced 23-1 to 23-q). The RESULT signal generated by the data compression unit 15 is applied to the input of "flag" latch 23-1, to the input of enabler logic 24, and to one input of (q+1)-way AND gate 25. The role of enabler logic 24, which essentially consists of AND gates, is to store an appropriate logic value in the "flag" latches 23-2 to 23-q so that at any time this logic value is stored in a predetermined "flag" latch, its corresponding fail address register is inhibited, i.e. it is prevented from receiving a new defective word address. This reasoning applies to "flag" latch 23-1 and to register 22-1, except that "flag" latch 23-1 is controlled by the RESULT signal. The outputs of flag latches 23-1 to 23-q are applied to the q remaining inputs of AND gate 25. Block 16A thus essentially consists of a bank of registers to store the defective word addresses. When all inputs of AND gate 25 are raised to a "1", the output signal, labelled COMPOSITE RESULT (CR), is likewise raised to "1", thus indicating that all registers have been filled. In block 16B, the CR signal generated by AND gate 25 is applied to the first input of 2-way OR gate 26 whose output is connected to latch 27. The output of latch 27 is attached to the second input of OR gate 26. This connection forms a self-locking loop, so that when latch 27 is set to a logic "1", its content can no longer be changed. Thus, block 16B is essentially a self-maintained fail register latch 27. Referring to block 16C, the RESULT signal is applied to the first input of 2-way OR gate 28, whose output is connected to latch 29. OR gate 28 and latch 29 are implemented in a similar manner to OR gate 26 and latch 27 of block 16B, as apparent from FIG. 2. Latch 29 is usually referred to as the "fail/no fail" latch.
Operation of the conventional fail address register 16 of FIG. 2 is as follows. During the course of a READ operation in the ABIST mode, the RESULT signal supplied by the data compression unit 15 and the STADD* signals supplied by ABIST unit 11 are used to memorize the defective word line addresses. At each cycle, address load register 21 receives the current word address from STADD*. On the following cycle, its content is presented in parallel to the input of all fail registers 22-1 to 22-q, but it is copied only to those fail address registers whose flag latches have not been locked. Due to the pipeline organization of the ABIST unit 11, register 21 is used to delay the STADD* signals by one cycle with respect to the RESULT signal. At each fail detected by data compression unit 15, the RESULT signal is raised to the "1" logic level and at the first fail, this information is saved in the "fail/no fail" latch 29. OR gate 28 is used in conjunction with "fail/no fail" latch 29 to save this information during the entirety of the ABIST mode, i.e., in either of the two manufacturing and system sub-modes. Simultaneously, the flag latch pair 23-1 is locked to a "1", and this value inhibits its corresponding fail register 22-1, i.e., it prevents any changes by deactivating its LSSD clock signal C. This fault detection process continues under the control of enabler logic 24 until register 22-q is reached. At each cycle, the intermediate results are combined in the AND gate 25 to generate the CR signal. If the number of defective word line addresses exceeds the number of available redundant word lines (or the fuse repair capabilities), on the following cycle, the CR signal is raised to the high level (logic "1"). This information is saved in latch 27, where it is maintained during the totality of the ABIST manufacturing sub-mode (and in the system sub-mode as well, except that in this case, the information is not used). When latch 27 is set to a "1", the memory unit 12 is considered "unfixable", and the product chip must be rejected. Dedicated latch 27 is usually referred to in the literature as a "not fixable" latch.
With the structure shown in of FIGS. 1 and 2, the current test methodology is illustrated by algorithm 30 (FIG. 3). Product chips at the wafer level stocked in box 31 are first tested in box 32, to identify initially good (IG), repairable (R), and bad (B) chips. Bad chips are rejected in box 33. Repairable chips are fixed in box 34 to allow the subsequent use of spare redundant word lines. As explained above by reference to FIG. 2, during the ABIST manufacturing sub-mode, addresses of defective word lines are identified and stored in the registers of fail address register unit 16. Then a SCAN mode is performed, the fail address registers 22-1 to 22-q forming the LSSD chain are unloaded and the addresses transferred to the tester. Finally, the defective word addresses are sent from the tester to a conventional fuse tool to be written in storage unit 19 using conventional laser fuse blow techniques. Each defective word address corresponds to a register in the fail register unit 16 and a row of fuses in storage unit 19. For each row, an additional "flag" fuse is provided which corresponds to the "flag" latch in fail address register unit 16, that indicates whether the defective word line is active. Once these defective word line addresses have been permanently stored in storage unit 19, the repaired chips are tested in box 35 to determine their functionality. Bad chips are rejected in box 33. Repaired good (RG) chips from box 35 and initially good (IG) chips from box 32 are submitted to the burn-in step in block 36 and tested in block 37. Depending on the results of the post burn-in or final test completed in block 37, only finally good (FG) chips are retained for shipment in block 38, while bad (B) chips are rejected from the production lots in box 33.
With the conventional technique described above, only a one-pass fuse blow is possible in the ABIST mode. A second pass fuse blow would not be possible after final test in block 34 because, had a fail been detected, there would be no way to identify its origin: whether in the regular array 12A' or in the redundant array 12A". A defective word line detected by ABIST 11 could possibly be located in redundant array 12A". Indeed, there is no known methodology to adequately test redundant array 12A". An iterative process for repairing the product chip is not possible, because if a defective word line that was already replaced by a redundant word line during the first pass has to be repaired in block 34, two redundant word lines would be mapped on the same word address. This is clearly not acceptable. Even if fuses are available for replacing the defective word line, the chip cannot be repaired and is considered defective, while in actuality, it could be repaired. Another problem is that there is no way to track whether some or all of the redundant addresses have already been used. As a result, ABIST 11 may indicate that the memory unit of a product chip is repairable, when in reality it is not. Presently, chips failing after a single pass laser fuse blow are rejected because it is not possible to determine whether all redundant lines were used. In all cases, the manufacturing yields are severely impacted.
In addition to the methodology of FIG. 3, there is no way of determining if a chip has already been repaired (unless a special marking/handling is performed), because initially good and repaired good chips are sorted and stocked in the same block 38. It is admitted that in the future, in the ABIST system sub-mode, should a fail appear during the lifetime of the chip operating in a system environment, it will be automatically repaired in situ using electrical fuses. (Electrical fuses are those that can be electrically blown, as opposed to conventional fuses that can only be laser blown using a complex laser tool.) It thus could be important in the future to distinguish initially good from repaired good product chips in that regards to allow self-repair during the lifetime of a chip.
All these drawbacks result from the limitation of the prior art technique based on a single pass fuse blow methodology. Consequently, for the reasons given above, it is highly desirable that a second pass fuse blow be made possible at the time the chip is manufactured and during its subsequent system environment. A second pass fuse blow provides not only a significant improvement in manufacturing yields, but also allows self-repair by in-situ reconfiguration of electrical fuses of the chip in a system environment. It, therefore, also improves the in-field serviceability of the system incorporating such chips.